.extern main
.text
.global _start
_start:
	b	reset			@ when reset, cpu jump to 0 address
	b	halt			@ldr	pc, _undefined_instruction
	b	halt			@ldr	pc, _software_interrupt
	b	halt			@ldr	pc, _prefetch_abort
	b	halt			@ldr	pc, _data_abort
	b	halt			@ldr	pc, _not_used
	ldr	pc, _irq
	b	halt			@ldr	pc, _fiq

_irq:
	.word vector_irq

vector_irq:

	bl	vector_irq			@ deal with exception

halt:
	b halt
/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0

    /* Peri port setup */
	ldr	r0, =0x70000000
	orr	r0, r0, #0x13
    mcr	p15,0,r0,c15,c2,4       @ 256M(0x70000000-0x7fffffff)

    /* Disable Watchdog */
	ldr	r0, =0x7e000000		@0x7e004000
	orr	r0, r0, #0x4000
	mov	r1, #0
	str	r1, [r0]

	bl	lowlevel_init

	ldr	sp, =0x0c000000		@ set stack, notice: can't larger than 8K
	orr sp, sp, #0x2000

	bl  main
